Associate Professor receives US Patent

May 14, 2015
Dr. Elias Kougianos

Warm congratulations to Dr. Elias Kougianos, associate professor, for being a co-inventor of US Patent 9,026,964, by S. Mohanty, E. Kougianos, and G. Zheng, issued on May 5, 2015:

Intelligent metamodel integrated Verilog-AMS for fast and accurate analog block design exploration

Abstract

A method for modeling a circuit comprising storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory. Performing transistor-level simulations at a plurality of sample points for the circuit component to generate a plurality of design variable samples for the circuit component. Storing a neural network architecture in the non-transient electronic data memory that models the plurality of design variable samples for the circuit component. Storing a performance metric metamodel and a circuit parameter metamodel generated using Verilog-AMS.